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AN3422 데이터시트(PDF) 36 Page - STMicroelectronics |
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AN3422 데이터시트(HTML) 36 Page - STMicroelectronics |
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36 / 52 page ![]() Peripheral migration AN3422 36/52 Doc ID 018976 Rev 2 Low-power modes Sleep mode Stop mode Standby mode (1.8V domain powered- off) RUN Low Power Sleep mode + peripherals automatic clock gating Sleep Low Power mode + peripherals automatic clock gating Stop mode Standby mode (VCORE domain powered off) Note: To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Wake-up sources Sleep mode – Any peripheral interrupt/wakeup event Stop mode – Any EXTI line event/interrupt Standby mode – WKUP pin rising edge –RTC alarm – External reset in NRST pin – IWDG reset Sleep mode – Any peripheral interrupt/wakeup event Stop mode – Any EXTI line event/interrupt Standby mode – WKUP pin rising edge – RTC alarm A, RTC alarm B, RTC Wakeup, Tamper event, TimeStamp event – External reset in NRST pin – IWDG reset Configuration NA In L1 some additional bits were added: – PWR_CR[ULP] used to switch off the VREFINT in STOP and STANDBY modes. – PWR_CR[FWU] used to ignore the VREFINT startup time when exiting from low power modes. – PWR_CR[VOS] used to select the product voltage range. – PWR_CR[LPRUN] used to select the RUN low power mode. – PWR_CSR[VREFINTRDY]: VREFTINT ready status – PWR_CSR[VOSF]: Internal Regulator change status – PWR_CSR[REGLP]: MCU is in Low power run mode – PWR_CSR[EWUP2] and PWR_CSR[EWUP3]: Wakeup Pin 2 and Wakeup Pin 3 Enable/Disable bits. Table 14. PWR differences between STM32F1 series and STM32L1 series (continued) PWR STM32F1 series STM32L1 series Color key: = New feature or new architecture = Same feature, but specification change or enhancement |
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