AN3422 datasheet(19/52 Pages) STMICROELECTRONICS

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AN3422

Peripheral migration

Doc ID 018976 Rev 2

19/52

APB1

frequency

up to 36 MHz

up to 32 MHz

No change to SW configuration:

configuration bits

RCC_CFGR[PPRE1].

APB2

frequency

up to 72 MHz

up to 32 MHz

No change to SW configuration:

configuration bits

RCC_CFGR[PPRE2].

RTC clock

source

LSI, LSE or HSE/128

LSI, LSE or HSE clock

divided by 2, 4, 8 or 16

RTC clock source configuration

is done through the same bits

(RTCSE[1:0] and RTCEN) but

they are located in a different

In L1 series the RTCSEL[1:0]

bits occupy bits

RCC_CSR[17:16] instead of bits

RCC_BDCR[9:8] in F1 series.

In L1 series the RTCEN bit

occupies bit RCC_CSR[22]

instead of bit RCC_BDCR[15] in

F1 series.

However, in L1 series when HSE

is selected as RTC clock source,

additional bits are used in CR

select the division factor to be

applied to HSE clock.

MCO clock

source

– MCO pin (PA8)

– Connectivity Line: HSI, HSE,

PLL/2, SYSCLK, PLL2, PLL3

or XT1

– Other product lines: HSI,

HSE, PLL/2 or SYSCLK

–MCO pin (PA8): SYSCLK,

HSI, HSE, PLLCLK, MSI,

LSE or LSI

With configurable prescaler,

1, 2, 4, 8 or 16 for each

output.

MCO configuration in L1 series

is different from F1:

– For MCO, the prescaler is

configured through bits

RCC_CFGR[MCOPRE] and

the selection of the clock to

output through bits

RCC_CFGR[MCOSEL]

Table 5.

RCC differences between STM32F1 and STM32L1 series (continued)

RCC main

features

STM32F1 series

STM32L1 series

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