RM0319 datasheet(229/368 Pages) STMICROELECTRONICS

229 / 368 page

RM0319

I2C bus ports (I2C)

Doc ID 022640 Rev 3

229/368

A hardware receiver does not respond to the START byte because it is a reserved address

and it resets after the Sr (restart condition) is generated.

17.3.3

DMA controller Interface

The I2C controller has a handshaking interface to request and control transfers from the

DMA controller of the SPEArTM device. The APB bus is used to perform the data transfer to

or from the DMA.

Note:

When the DMA controller of the SPEArTM device is used for data transfers to/from the I2C

controller, the DMA controller must always be programmed as the flow controller; that is, the

DMA controller controls the block size.

Enabling the DMA controller Interface

To enable the DMA controller interface on the I2C, the DMA Control Register (IC_DMA_CR)

has to be set. Writing a 'b1 into the TDMAE bit field of IC_DMA_CR register, it enables the

I2C controller transmit handshaking interface. Besides, writing a 'b1 into the RDMAE bit field

of the IC_DMA_CR register, the I2C controller receive handshaking interface is enabled.

Transmit Watermark Level and Transmit FIFO Underflow

During I2C controller serial transfers, transmit FIFO requests are made to the DMA

controller whenever the number of entries in the transmit FIFO is less than or equal to the

DMA Transmit Data Level Register (IC_DMA_TDLR) value, this is known as the "watermark

level".

The DMA controller responds by writing a burst of data to the transmit FIFO buffer. Data

should be written by the DMA often enough for the transmit FIFO to perform serial transfers

continuously; that is, when the FIFO begins to empty another DMA request should be

triggered. Otherwise, the FIFO will run out of data (underflow). To prevent this condition, the

user must set the watermark level correctly.

Choosing the Transmit Watermark Level

Choosing a watermark level can minimize the number of transactions per block, keeping the

probability of an underflow condition to an acceptable level.

In practice, this is a function of the ratio of the rate at which the I2C transmits data to the rate

at which the DMA can respond to destination burst requests. For example, promoting the

channel to the highest priority channel in the DMA, and promoting the DMA master interface

to the highest priority master in the AMBA layer, increases the rate at which the DMA

controller can respond to burst transaction requests. This in turn allows the user to decrease

the watermark level, which improves bus utilization without compromising the probability of

an underflow occurring.

Receive Watermark Level and Receive FIFO Overflow

During I2C controller serial transfers, receive FIFO requests are made to the DMA controller

whenever the number of entries in the receive FIFO is at or above the DMA Receive Data

Level Register (IC_DMA_RDLR), that is DMARDLR + 1, which is known as the "watermark

level".

The DMA controller responds by fetching a burst of data from the receive FIFO buffer. Data

should be fetched by the DMA often enough for the receive FIFO to accept serial transfers

continuously; that is, when the FIFO begins to fill, another DMA transfer is requested.

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