RM0319 datasheet(231/368 Pages) STMICROELECTRONICS

231 / 368 page

RM0319

I2C bus ports (I2C)

Doc ID 022640 Rev 3

231/368

Slave-transmitter operation

When another master addresses the I2C controller to requests data, the I2C controller acts

as a slave-transmitter, and the following steps occur:

●

The other master initiates an I2C transfer with an address that matches the slave

address in the IC_SAR register of the slave I2C controller (programmed during initial

configuration),

●

The I2C controller acknowledges the sent address and recognizes the direction of

transfer to indicate that it is acting as a slave-transmitter,

●

The I2C controller asserts the RD_REQ interrupt, (and relevant bit in

IC_RAW_INTR_STAT register is set) and holds the SCL line low, placing in a wait state

until software responds,

●

If there is any data remaining in the Transmit FIFO before receiving the read request,

then the I2C controller asserts a TX_ABRT interrupt, section, (and relevant bit in

IC_RAW_INTR_STAT register is set) to flush the old data from the Transmit FIFO,

●

Software then writes the IC_DATA_CMD register with the data to be written, setting to

1‘b0 the CMD bit (meaning a write operation),

●

Software should clear the RD_REQ and the TX_ABRT interrupts before proceeding,

●

The I2C controller releases the SCL and transmits the byte,

●

Finally, the master may hold the I2C bus by issuing a restart condition or release the

bus by issuing a stop condition.

Slave-receiver operation

When another master addresses the I2C controller to send its data, the I2C controller acts

as a slave-receiver and the following steps occur:

●

The other master initiates an I2C transfer with an address that matches the I2C

controller slave address in the IC_SAR register, programmed during initial

configuration,

●

The I2C controller acknowledges the sent address and recognizes the direction of

transfer to indicate that it is acting as a slave-receiver,

●

The I2C controller receives the transmitted byte from the master and place it in the

receive buffer, assuming there is room for this incoming data,

●

The status and interrupt bits corresponding to the receive buffer are updated,

●

Software may read the received byte from the IC_DATA_CMD register, setting to 1‘b1

the CMD bit (meaning a read operation),

●

Finally, the other master may hold the I2C bus by issuing a restart condition or release

the bus by issuing a stop condition.

Slave bulk transfer mode

In the standard I2C protocol, all transaction are single byte transactions and a remote

master read request is replied by writing one byte into the transmit FIFO.

In the mode named slave bulk transfer, if the remote master acknowledged the sent byte to

request more data, then the slave must hold the I2C SCL line low and request another byte

from the processor side. If it is known in advance that the remote master is requesting a

packet of n bytes, then when another master addresses the I2C controller and request data,

the Transmit FIFO could be written with 16 number of bytes and the remote master will

receive it as a continuous stream of data.

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