RM0319 datasheet(262/368 Pages) STMICROELECTRONICS

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Basic general purpose I/Os (basGPIO)

RM0319

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Doc ID 022640 Rev 3

Figure 93.

GPIO signal interfaces

22.3.2

Interrupt detection logic

The interrupt detection logic of the GPIO block which allows to generate mask-

programmable interrupts based on either the signal level or the transitional value (edge) of

any of the basGPIO lines.

As depicted in Figure 92, this block interfaces with both the interrupt control registers hosted

by the APB slave and the input signals from pad (GPIN[5:0]). Depending on registers

configuration (see Section 22.4.2: Control interrupt generation for details) and actual input

signals features, a GPIO interrupt signal (GPIOINTR) is generated by the Interrupt

Detection Logic block as the OR combination of all the GPIO masked interrupt lines.

The resulting combined GPIOINTR signal can be then used to indicate to an external

interrupt controller that an interrupt occurred in one or more of the basGPIO lines. Additional

output signals (GPIOMIS[5:0]) are also generated by the interrupt detection logic block,

reflecting the status of each single masked interrupt lines. Provisional of individual outputs

as well as combined interrupt output allows to use either a global interrupt service routine

(trapping the GPIOINTR signal) or modular device drivers (looking at GPIOMIS[5:0]) to

handle GPIO interrupts.

Table 74.

GPIO signal interface

Group

Signal name

Direction

Size

(bit)

Description

External

(to chip pads)

nGPEN

Output

Output pad enable signal (active low)

GPOUT

Output

Output pad data signal driver

GPIN

Input

Input data from chip pad

Interrupt

(on-chip)

GPIOMIS

Output

Masked interrupt signals, to interrupt

controller

GPIOINTR

Output

Combined OR version of GPIOMIS, to

interrupt controller

GPIO

APB Slave

SPI CS Selector

External(To Chip PAD)

Interrupt (On chip)

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