RM0319 datasheet(266/368 Pages) STMICROELECTRONICS

266 / 368 page

Extended general purpose I/O (PL_GPIO)

RM0319

266/368

Doc ID 022640 Rev 3

The GPIO functionality is independent of any of the functional modes listed in Section 32.2:

I/O multiplexing scheme configuration (whether legacy or extended).

When a pin is enabled as GPIO (through GPIO_SELECTx register), it can be used it as

GPIO_out, GPIO_in or interrupt with programmable edge detection.

●

The status of each of the edge-programmable GPIO interrupts can be read from the

GPIO_IRQx registers. The combined status is indicated by NGPIO_INTR (bit 6 of the

IrqStatus_Reg.

●

For backward compatibility with legacy designs, the interrupt status of each of the

“rising-edge only” GPIO interrupts can be read from the GPIO_MASKED_INTx

registers. Their combined status is indicated by the GPIO_INTR (bit 0 of the

IrqStatus_Reg).

In both of the above cases, GPIO interrupts are available when the I/O is selected as GPIO,

independent of any functional mode. The GPIO_IRQ_MASKx registers mask GPIO

interrupts in all modes.

When using Extended mode, you can also configure some pins as GPIO input by

programming the RAS_iosel_reg registers. This is possible in those cases where the pin

multiplexing is not fully used for other signals.

23.2.1

PL_GPIO external interrupts

In GPIO input mode, interrupts can be enabled by clearing the corresponding mask bit in the

GPIO interrupt mask registers.

Interrupt polarity can be selected as rising edge or falling edge in the GPIO edge polarity

registers.

When a interrupt event occurs on one of the PL_GPIO pins an interrupt status flag is set in

the corresponding bit of the GPIO interrupt status registers.

All the GPIO interrupts are ORed into a single interrupt request (IRQ30) sent to the vectored

interrupt controller (VIC).

The interrupt flags can be cleared by writing 0 in the corresponding bit of the GPIO interrupt

status register

Example:

To enable GPIO_43 for edge interrupt detection, the following registers need to be

programmed:

1. Enable RAS_GPIOs (select RAS functionality)

RAS_Select_REG &= 0xFFFFFFFE;

2. Enable pin as GPIO

GPIO_SELECT1 |= 0x800;

3. Enable GPIO as input

GPIO_EN1 |= 0x800;

4. Edge programming for interrupts

GPIO_IRQ_EDGE1 |= 0x800;

-> rising edge detection

GPIO_IRQ_EDGE1 &= 0xFFFFF7FF;

-> falling edge detection

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