| 전자부품 데이터시트 검색엔진 |
|
RM0319 데이터시트(PDF) 293 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
RM0319 데이터시트(HTML) 293 Page - STMicroelectronics |
|
293 / 368 page ![]() RM0319 Digital audio port (I2S) Doc ID 022640 Rev 3 293/368 27.4.3 Audio data interface The default value of audio data for the TX/RX Channel is 32 bits. It can be reprogrammed during operation to any supported audio data resolution that is less than 32 bits. Valid values: 12, 16, 20, 24, or 32 bits. Changes to the resolution are programmed my means of the word length (WLEN) bits of the transmitter/receive configuration registers (TCR0[2:0]/RCR0[2:0]. The channel must be disabled prior to any resolution changes. 27.4.4 External I2S_CLK gating and enable signal When the audio data resolution of the receive and transmit channels is less than the current word select size, the I2S_CLK can be gated off for the remainder of the left/right cycle. This can be programmed during operation of the component by setting the I2S_CLK Gating (SCLKG) bits [2:0] in the Clock Configuration Register (CCR). The clock generation block must be disabled prior to any changes to I2S_CLK gating value. 27.5 Clocks Figure 104. I2S clocks PLL2 RAS_CLK_SYNT3 Clksel (from configuration registers) DIV4 sclk I2S audio_over_samp_clk I2S_CLK I2S_LR I2S_TX I2S_RX |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |