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AN4471 데이터시트(PDF) 12 Page - STMicroelectronics |
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AN4471 데이터시트(HTML) 12 Page - STMicroelectronics |
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12 / 39 page ![]() Hardware layout and configuration AN4471 12/39 DocID026197 Rev 1 Figure 6. Acquisition by Program “0”, where C1, C2, C3 and C4 are XDCR_1, XDCR_2, XDCR_3 and XDCR_4, respectively 3.4.3 Pattern Program 1 The second pattern stored in the SPI Flash is described in Table 10, where the output pulses are delayed by 10 ns each. Its state sequence is indicated in Table 11. In order to appreciate the waveforms shown in Table 7 and Table 8, the following test conditions have been applied: – HVP0 = + 80 V – HVM0 = - 80 V – Load: 300 pF // 100 Ω Table 10. Program “1” Mode Frequency [MHz] Number of pulses Initial pulse PRF H-Bridge XDCR_1 PW 5 10 positive 300 µs HV_TX XDCR_2 PW 5 10 negative 300 µs HV_TX XDCR_3 PW 5 10 positive 300 µs HV_TX XDCR_4 PW 5 10 negative 300 µs HV_TX XDCR_5 PW 5 10 positive 300 µs HV_TX XDCR_6 PW 5 10 negative 300 µs HV_TX XDCR_7 PW 5 10 positive 300 µs HV_TX XDCR_8 PW 5 10 negative 300 µs HV_TX |
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