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AN4471 데이터시트(PDF) 16 Page - STMicroelectronics |
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AN4471 데이터시트(HTML) 16 Page - STMicroelectronics |
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16 / 39 page ![]() Hardware layout and configuration AN4471 16/39 DocID026197 Rev 1 Figure 9. Acquisition by Program “2”, where C1, C2, C3 and C4 are XDCR_1, XDCR_2, XDCR_3 and XDCR_4, respectively 3.4.5 Pattern Program 3 The fourth pattern stored in the SPI Flash is described in Table 14, where the output pulses are in delayed by 10 ns each. Its state sequence is indicated in Table 15. In order to appreciate the waveforms shown in Figure 10 and Figure 11, the following test conditions have been applied: – HVP_CW = + 10 V – HVM_CW = - 10 V – Load: 300 pF // 100 Ω Table 14. Program “3” Mode Frequency [MHz] Number of pulses Initial pulse H-Bridge XDCR_1 CW 5 continuous wave positive HV-CW XDCR_2 CW 5 continuous wave positive HV-CW XDCR_3 CW 5 continuous wave positive HV-CW XDCR_4 CW 5 continuous wave positive HV-CW XDCR_5 CW 5 continuous wave positive HV-CW XDCR_6 CW 5 continuous wave positive HV-CW XDCR_7 CW 5 continuous wave positive HV-CW XDCR_8 CW 5 continuous wave positive HV-CW |
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