AN4471 datasheet(19/39 Pages) STMICROELECTRONICS

19 / 39 page

DocID026197 Rev 1

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AN4471

Hardware layout and configuration

3.4.6

Pattern Program 4

The fifth pattern stored in the SPI Flash is described in Table 16, where the output pulses

are in phase. Its state sequence is indicated in Table 17. In order to appreciate the

waveforms shown in Figure 12 and Figure 13, the following test conditions have been

applied:

– HVP = +80 V

– HVM = -80 V

– Load: 300pF // 100

Ω

Table 16. Program “4”

Mode

Frequency

[MHz]

Number of

pulses

Initial pulse

PRF

H-Bridge

XDCR_1

2.5

positive

300 µs

HV_TX

XDCR_2

2.5

negative

300 µs

HV_TX

XDCR_3

positive

300 µs

HV_TX

XDCR_4

negative

300 µs

HV_TX

XDCR_5

2.5

positive

300 µs

HV_TX

XDCR_6

2.5

negative

300 µs

HV_TX

XDCR_7

positive

300 µs

HV_TX

XDCR_8

negative

300 µs

HV_TX

Table 17. State sequence Program “4”

XDCR_1

XDCR_2

XDCR_3

XDCR_4

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

HVP

200 ns

HVM

200 ns

HVP

100 ns

HVM

100 ns

HVM

200 ns

HVP

200 ns

HVM

100 ns

HVP

100 ns

HVP

200 ns

HVM

200 ns

HVP

100 ns

HVM

100 ns

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

295.4 µs

295.7 µs

XDCR_5

XDCR_6

XDCR_7

XDCR_8

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

HVP

200 ns

HVM

200 ns

HVP

100 ns

HVP

100 ns

HVM

200 ns

HVP

200 ns

HVM

100 ns

HVM

100 ns

CLAMP

2 µs

CLAMP

2 µs

CLAMP

2 µs

HVP

2 µs

295.6 µs

295.8 µs

HVM

295.8 µs

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