UPD72001C datasheet(3/40 Pages) NEC

3 / 40 page

µPD72001-11, 72001-A8

SPECIFICATIONS

Item

Specifications

Part number

µPD72001-11

µPD72001-A8

Supply voltage

5 V

±10 %

3.3 V

±0.3 V

System clock frequency

11 MHz MAX.

8 MHz MAX. (at TA = –10 to +70

°C)

7.14 MHz MAX. (at TA = –40 to +85

°C)

Maximum transfer rate

2.2 Mbps

1.6 Mbps (at TA = –10 to +70

°C)

1.43 Mbps (at TA = –40 to +85

°C)

Process

CMOS

Internal circuit

Parallel/serial converter circuit: Full-duplex channel

× 2

Transmit buffer : Double

Receive buffer : Quadruple

Interrupt control function

DMA request signal output: 2 for transmission, 2 for reception

Overrun error detection

DPLL

Baud rate generator

Crystal oscillation circuit for transmission/reception clock generation

Self-loopback test function

Standby function

General-purpose I/O pin: 4 pins

× 2

Communication protocol

Start-stop

Character bit length: 5, 6, 7, 8

synchronization

Stop bit length: 1, 1.5, 2

Clock rate:

×1, ×16, ×32, ×64

Parity generation, check

Framing error detection

Break generation, detection

COP

Operation mode: Mono-sync, Bi-sync, External sync

(Character

Character bit length: 5, 6, 7, 8

Oriented

SYNC character bit length: 6, 8

Protocol)

Character synchronization: Internal/external

BCS (Block Check Sequence) generation, check:

CRC-16

CRC-CCITT

Parity generation, check

SYNC character automatic transmission, detection, rejection

BOP

Operation mode:

(Bit Oriented

HDLC (High-level Data Link Control)

Protocol)

SDLC (Synchronous Data Link Control)

SDLC Loop

Flag transmission, detection

Zero insertion, rejection

Address field detection (1 byte)

FCS (Frame Check Sequence) generation, detection

Short frame detection

Abort automatic transmission, detection

Idle detection

Go Ahead detection

Transmit number data control

Processing data format

Encode/decode of NRZ (Non-Return to Zero)

Encode/decode of NRZI (Non-Return to Zero Inverted)

Encode/decode of FM (Frequency Modulation)

Decode in Manchester mode

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