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UPD72001C 데이터시트(PDF) 22 Page - NEC

부품명 UPD72001C
상세설명  MULTI-PROTOCOL SERIAL CONTROLLERS
PDF  40 Pages
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
Logo NEC - NEC

UPD72001C 데이터시트(HTML) 22 Page - NEC

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µPD72001-11, 72001-A8
22
Serial control:
Parameter
Symbol
Condition
Rated Value
Unit
MIN.
MAX.
Transmit/receive data cycle
tCYD
5tCYK
STRXC, TRXC input clock cycle
tCYC
TA = –10 to +70
°C
125
DC
ns
TA = –40 to +85
°C
140
DC
ns
STRXC, TRXC input
tWCH
High level
TA = –10 to +70
°C50
DC
ns
clock pulse width
TA = –40 to +85
°C55
DC
ns
tWCL
Low level
TA = –10 to +70
°C60
DC
ns
TA = –40 to +85
°C65
DC
ns
STRXC, TRXC
↓ → delay time
tDTCTD1
×1 mode, COP,
TA = –10 to +70
°C
140
ns
BOP
TA = –40 to +85
°C
145
ns
tDTCTD2
×16, 32, 64 mode
TA = –10 to +70
°C
300
ns
TA = –40 to +85
°C
305
ns
TRXC
↓ → TxD delay time
tDTCTD3
TRXC is output
0
100
ns
RXD setup time (vs. STRXC, TRXC
↑)tSRDRC
When DPLL is
TA = –10 to +70
°C0
ns
not used
TA = –40 to +85
°C5
ns
RXD hold time (vs. STRXC, TRXC
↑)tHRCRD
When DPLL is
TA = –10 to +70
°C
140
ns
not used
TA = –40 to +85
°C
145
ns
RXD
→ TXD delay time
tDRDTD1
ECHO BACK mode
100
ns
tDRDTD2
Without SDLC Loop delay
100
ns
TXD
→ INT delay time
tDTDIQ
TX INT mode
4
6
tCYK
TXD
→ DRQTX delay time
tDTDDQ
TX DMA mode
4
6
tCYK
RxC
↑ Note → INT delay time
tDRCIQ
RX INT mode
7
11
tCYK
RxC
↑ Note → DRQRX delay time
tDRCDQ
RX DMA mode
7
11
tCYK
RD
↓ → DRQRX ↓ delay time
tDRDQ
140
ns
WR
↓ → DRQTX ↓ delay time
tDWDQ
140
ns
Note Of STRXC and TRXC, the one used as the receive clock.



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