ISPMACH4ACPLDFAMILY datasheet(6/62 Pages) LATTICE

6 / 62 page

ispMACH 4A Family

Table 4. Architectural Summary of ispMACH 4A devices

The Macrocell-I/O cell ratio is deﬁned as the number of macrocells versus the number of I/O

cells internally in a PAL block (Table 4).

The central switch matrix takes all dedicated inputs and signals from the input switch matrices

and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block

still must go through the central switch matrix. This mechanism ensures that PAL blocks in

ispMACH 4A devices communicate with each other with consistent, predictable delays.

The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL

devices on a single chip. It allows the designer to think of the device not as a collection of

blocks, but as a single programmable device; the software partitions the design into PAL blocks

through the central switch matrix so that the designer does not have to be concerned with the

internal architecture of the device.

Each PAL block consists of:

x Product-term array

x Logic allocator

x Macrocells

x Output switch matrix

x I/O cells

x Input switch matrix

x Clock generator

Notes:

1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.

ispMACH 4A Devices

M4A3-64/32, M4A5-64/32

M4A3-96/48, M4A5-96/48

M4A3-128/64, M4A5-128/64

M4A3-192/96, M4A5-192/96

M4A3-256/128, M4A5-256/128

M4A3-384

M4A3-512

M4A3-32/32

M4A5-32/32

M4A3-64/64

M4A3-256/160

M4A3-256/192

Macrocell-I/O Cell

Ratio

2:1

1:1

Input Switch Matrix

Yes

Yes1

Input Registers

Yes

Central Switch Matrix

Yes

Output Switch Matrix

Yes

ISPMACH4ACPLDFAMILY 데이터시트(PDF) 6 Page - Lattice Semiconductor

ISPMACH4ACPLDFAMILY 데이터시트(HTML) 6 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

데이터시트 다운로드

링크 URL