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ISPMACH4ACPLDFAMILY 데이터시트(PDF) 11 Page - Lattice Semiconductor

부품명 ISPMACH4ACPLDFAMILY
상세설명  High Performance E 2 CMOS In-System Programmable Logic
PDF  62 Pages
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제조업체  LATTICE [Lattice Semiconductor]
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ISPMACH4ACPLDFAMILY 데이터시트(HTML) 11 Page - Lattice Semiconductor

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ispMACH 4A Family
11
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be
synthesized. The primary flip-flop configurations are shown in Figure 6, although others are
possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will
cause oscillation if both J and K inputs are HIGH.
DQ
AP AR
DQ
AP AR
LQ
AP AR
LQ
AP AR
G
G
TQ
AP AR
17466G-011
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
a. D-type with XOR
b. D-type with programmable D polarity
c. Latch with XOR
d. Latch with programmable D polarity
e. T-type with programmable T polarity
f. Combinatorial with XOR



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