PIC16F628-20SLASHSS datasheet(51/160 Pages) MICROCHIP

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Preliminary

DS40300B-page 51

PIC16F62X

7.1

Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

7.2

Timer1 Operation in Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode the timer increments on every rising edge of

clock input on pin RB7/T1OSI when bit T1OSCEN is

set or pin RB6/T1OSO/T1CKI when bit T1OSCEN is

cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The pres-

caler stage is an asynchronous ripple-counter.

In this configuration, during SLEEP mode, Timer1 will

not increment even if the external clock is present,

since the synchronization circuit is shut off. The pres-

caler however will continue to increment.

7.2.1

EXTERNAL CLOCK INPUT TIMING FOR

SYNCHRONIZED COUNTER MODE

When an external clock input is used for Timer1 in syn-

chronized counter mode, it must meet certain require-

ments. The external clock requirement is due to

internal phase clock (Tosc) synchronization. Also, there

is a delay in the actual incrementing of TMR1 after syn-

chronization.

When the prescaler is 1:1, the external clock input is

the same as the prescaler output. The synchronization

of T1CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T1CKI to be high for at least 2Tosc (and

a small RC delay of 20 ns) and low for at least 2Tosc

(and a small RC delay of 20 ns). Refer to the appropri-

ate electrical specifications, parameters 45, 46, and 47.

When a prescaler other than 1:1 is used, the external

clock input is divided by the asynchronous rip-

ple-counter type prescaler so that the prescaler output

is symmetrical. In order for the external clock to meet

the sampling requirement, the ripple-counter must be

taken into account. Therefore, it is necessary for T1CKI

to have a period of at least 4Tosc (and a small RC delay

of 40 ns) divided by the prescaler value. The only

requirement on T1CKI high and low time is that they do

not violate the minimum pulse width requirements of

10 ns). Refer to the appropriate electrical specifica-

tions, parameters 40, 42, 45, 46, and 47.

FIGURE 7-1:

TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

clock input

RB6/T1OSO/T1CKI

RB7/T1OSI

Note 1:

When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set flag bit

TMR1IF on

Overflow

TMR1

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