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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC16F628-20/SS 데이터시트(PDF) 81 Page - Microchip Technology |
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PIC16F628-20/SS 데이터시트(HTML) 81 Page - Microchip Technology |
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81 / 160 page  © 1999 Microchip Technology Inc. Preliminary DS40300B-page 81 PIC16F62X FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT FIGURE 12-10: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FIGURE 12-11: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY VALID DATA BYTE Start bit bit1 bit0 bit8 bit0 Stop bit Start bit bit8 Stop bit RC7/RX/DT (pin) Rcv buffer reg Rcv shift reg Read Rcv buffer reg RCREG RCIF (interrupt flag) WORD 1 RCREG Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) Bit8 = 0, Data Byte Bit8 = 1, Address Byte because ADEN = 1 and bit8 = 0. ADEN = 1 (address match enable) ’1’ ’1’ Start bit bit1 bit0 bit8 bit0 Stop bit Start bit bit8 Stop bit RC7/RX/DT (pin) reg Rcv buffer reg Rcv shift Read Rcv buffer reg RCREG RCIF (interrupt flag) WORD 1 RCREG Bit8 = 1, Address Byte Bit8 = 0, Data Byte Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG (receive buffer) because ADEN was not updated (still = 1) and bit8 = 0. ADEN = 1 (address match enable) ’1’ ’1’ Start bit bit1 bit0 bit8 bit0 Stop bit Start bit bit8 Stop bit RC7/RX/DT (pin) reg Rcv buffer reg Rcv shift Read Rcv buffer reg RCREG RCIF (interrupt flag) WORD 2 RCREG Bit8 = 1, Address Byte Bit8 = 0, Data Byte Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG (receive buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of the receive shift register (RSR) are read into the receive buffer regardless of the value of bit8. ADEN (address match enable) WORD 1 RCREG |
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