W97AH6KB datasheet(97/127 Pages) WINBOND

97 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 97 -

8.2.6.7

Input/Output Capacitance

Table of Input/Output Capacitance

Parameter

Symbol

Min

Max

Units

Note

Package Input capacitance, CK_t and CK_c

CPKGCK

1, 2

Package Input capacitance delta, CK_t and CK_c

CDPKGCK

0.2

1, 2, 3

Package Input capacitance, all other input-only pins

CPKGI

1, 2, 4

Package Input capacitance delta, all other input-only pins

CDPKGI

-0.5

0.5

1, 2, 5

Package Input/output capacitance, DQ, DM, DQS_t, DQS_c

CPKGIO

1.25

3.5

1, 2, 7

Package Input/output capacitance delta, DQS_t, DQS_c

CDPKGDQS

0.25

1, 2, 6

Package Input/output capacitance delta, DQ, DM

CDPKGIO

-0.5

0.5

1, 2, 7

Package Input/output capacitance, ZQ Pin

CPKGZQ

3.5

1, 2

(TOPER; VDDQ = 1.14- 1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, LPDDR2-S4 VDD2 = 1.14-1.3V).

Notes:

This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to

JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSCA, VSSQ

applied and all other pins floating.

This parameter applies to package only (does not include die capacitance). This value is vendor specific.

Absolute value of CPKGCK_t - CPKGCK_c.

CPKGI applies to CS_n, CKE, CA0-CA9

CDPKGI = CPKGI - 0.5 * (CPKGDQS_t + CPKGDQS_c).

Absolute value of CPKGDQS_t and CPKGDQS_c.

CDPKGIO = CPKGIO - 0.5 * (CPKGDQS_t + CPKGDQS_c) in byte lane.

Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other LPDDR2 devices: 5 pF.

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