FXLS8471Q datasheet(35/75 Pages) FREESCALE

35 / 75 page

FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

10.1.10 CTRL_REG3 [Interrupt Control Register] (0x2C) register

Table 36. CTRL_REG3 register

fifo_gate

wake_trans

wake_lndprt

wake_pulse

wake_ffmt

wake_en_a_vecm

ipol

pp_od

Table 37. CTRL_REG3 bit descriptions

Field

Description

fifo_gate

0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from Wake-to-Sleep mode or from Sleep-

to-Wake mode.

1: The FIFO input buffer is blocked when transitioning from “Wake-to-Sleep” mode or from “Sleep-to-Wake” mode until

the FIFO is flushed.(1) Although the system transitions from “Wake-to-Sleep” or from “Sleep-to-Wake” the contents of the

FIFO buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application.

If the fifo_gate bit is set to logic ‘1’ and the FIFO buffer is not emptied before the arrival of the next sample, then the

SYSMOD[fgerr] will be asserted. The SYSMOD[fgerr] bit remains asserted as long as the FIFO buffer remains un-

emptied.

Emptying the FIFO buffer clears the SYS_MOD[fgerr] register.

1. The FIFO contents are flushed whenever the system ODR changes in order to prevent the mixing of FIFO data from different ODR periods.

wake_tran

0: Transient function is disabled in Sleep mode

1: Transient function is enabled in Sleep mode and can generate an interrupt to wake the system

wake_lndprt

0: Orientation function is disabled Sleep mode.

1: Orientation function is enabled in Sleep mode and can generate an interrupt to wake the system

wake_pulse

0: Pulse function is disabled in Sleep mode

1: Pulse function is enabled in Sleep mode and can generate an interrupt to wake the system

wake_ffmt

0: Freefall/motion function is disabled in Sleep mode

1: Freefall/motion function is enabled in Sleep mode and can generate an interrupt to wake the system

wake_en_a_vecm

0: Acceleration vector-magnitude function is disabled in Sleep mode

1: Acceleration vector-magnitude function is enabled in Sleep mode and can generate an interrupt to wake the system

ipol

The ipol The bit selects the logic polarity of the interrupt signals output on the INT1 and INT2 pins.

INT1/INT2 interrupt logic polarity:

0: Active low (default)

1: Active high

pp_od

INT1/INT2 push-pull or open-drain output mode selection. The open-drain configuration can be used for connecting

multiple interrupt signals on the same interrupt line but will require an external pullup resistor to function correctly.

0: Push-pull (default)

1: Open-drain

FXLS8471Q 데이터시트(PDF) 35 Page - Freescale Semiconductor, Inc

FXLS8471Q 데이터시트(HTML) 35 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

데이터시트 다운로드

링크 URL