XC164CS datasheet(60/71 Pages) INFINEON

60 / 71 page

XC164

Derivatives

Timing Parameters

Data Sheet

V2.1, 2003-06

Timing Parameters

5.1

Definition of Internal Timing

The internal operation of the XC164 is controlled by the internal master clock

fMC.

The master clock signal

fMC can be generated from the oscillator clock signal fOSC via

different mechanisms. The duration of master clock periods (TCMs) and their variation

(and also the derived external timing) depend on the used mechanism to generate

fMC.

This influence must be regarded when calculating the timings for the XC164.

Figure 15

Generation Mechanisms for the Master Clock

Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,

the example for prescaler operation refers to a divider factor of 2:1.

The used mechanism to generate the master clock is selected by register PLLCON.

CPU and EBC are clocked with the CPU clock signal

fCPU. The CPU clock can have the

same frequency as the master clock (

fCPU = fMC) or can be the master clock divided by

two:

fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.

The specification of the external timing (AC Characteristics) depends on the period of the

CPU clock, called “TCP”.

The other peripherals are supplied with the system clock signal

fSYS which has the same

frequency as the CPU clock signal

fCPU.

TCM

fMC

fOSC

fMC

fOSC

Phase Locked Loop Operation (1:N)

Direct Clock Drive (1:1)

TCM

fMC

fOSC

Prescaler Operation (N:1)

XC164CS 데이터시트(PDF) 60 Page - Infineon Technologies AG

XC164CS 데이터시트(HTML) 60 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

데이터시트 다운로드

링크 URL