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XC164CS 데이터시트(PDF) 63 Page - Infineon Technologies AG |
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XC164CS 데이터시트(HTML) 63 Page - Infineon Technologies AG |
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63 / 71 page ![]() XC164 Derivatives Timing Parameters Data Sheet 59 V2.1, 2003-06 5.2 External Clock Drive XTAL1 Figure 17 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). Table 16 External Clock Drive Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit min. max. Oscillator period tOSC SR 20 2501) 1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL. ns High time2) 2) The clock input signal must reach the defined levels VILC and VIHC. t1 SR 6 – ns Low time2) t2 SR 6 – ns Rise time2) t3 SR – 8 ns Fall time2) t4 SR – 8 ns MCT05138 3 t 4 t VIHC VILC V DDI 0.5 1 t 2 t OSC t |
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