USB3803 datasheet(42/99 Pages) MICROCHIP

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USB3803

DS00001691B-page 42

 2014-2015 Microchip Technology Inc.

6.0

SERIAL SLAVE INTERFACE

6.1

Overview

The serial slave interface on USB3803 is implemented as I2C. It is a standard I2C slave interface that operates at the

standard (100Kbps), fast (400Kbps), and the fast mode plus (1Mbps) modes.

The USB3803 I2C slave interface supports four 7-bit slave addresses. Address selection is done through values set on

the I2C_ASEL1 and I2C_ASEL0 pins during the HUB.INIT stage as shown in Table 6-1, "Serial Slave Address Selec-

tion".

REFCLK must be running for I2C to operate. The register map is outlined in section Section 5.3.

Two I2C Slave Base Addresses will be programmed into ROM and selected with the I2C_ASEL1 pin. The LSB of the

serial slave address is selected with the I2C_ASEL0 pin. Table 6-1, "Serial Slave Address Selection" shows resulting

I2C address based on I2C_ASEL pin settings and default ROM programmed register values. In the table bits a6-1 rep-

resent bits programmed into register I2CADD0 and bits b6-1 represent bits programmed into register I2CADD1. Detailed

definition can be found in Section 5.3.33, "Register EAh: I2C Address 0 - I2CADD0," on page 34 and Section 5.3.34,

"Register EBh: I2C Address 1 - I2CADD1," on page 35. Table 6-2 shows a specific example of the resulting addresses

with two specific examples of default control register values. The addresses are shown both in binary and hexadecimal

format in parenthesis for clarity.

TABLE 6-2:

EXAMPLE SERIAL SLAVE ADDRESSES

The interrupt pin INT_N is used to communicate status changes on selected events which are mapped into the Serial

Port Interrupt Status Register. The SOC can mask events to not cause the interrupt pin to transition by updating the

Serial Port Interrupt Mask Register- the status events will still be captured in the status register even if the interrupt pin

is not asserted. The serial port has limited speed and latency capability so events mapped into the serial ports and its

interrupt are not expected to be latency critical.

INT_N is asserted low whenever an unmasked bit is set in the Serial Port Interrupt Status Register. SOC must update

the Serial Port Interrupt Status Register to negate the interrupt high.

TABLE 6-1:

SERIAL SLAVE ADDRESS SELECTION

I2C_ASEL1

I2C_ASEL0

I2CADD0 Register Value I2CADD1 Register Value

Functional I2C Address

Result

0a6a5a4a3a2a10

don’t care

a6a5a4a3a2a10

0a6a5a4a3a2a10

don’t care

a6a5a4a3a2a11

don’t care

0b6b5b4b3b2b10b6b5b4b3b2b10

don’t care

0b6b5b4b3b2b10b6b5b4b3b2b11

I2C_ASEL1

I2C_ASEL0

Example I2CADD0

Example I2CADD1

Functional I2C

Address Result

0001000 (0x08)

00101000 (0x28)

0001000 (0x08)

00101000 (0x28)

0001001 (0x09)

0001000 (0x08)

00101000 (0x28)

0101000 (0x28)

0001000 (0x08)

00101000 (0x28)

0101001 (0x29)

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