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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MEC1322 데이터시트(PDF) 240 Page - Microchip Technology |
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MEC1322 데이터시트(HTML) 240 Page - Microchip Technology |
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240 / 456 page  MEC1322 DS00001719D-page 240 2014 - 2015 Microchip Technology Inc. 19.11.14 REGISTER D 19.11.15 RTC CONTROL REGISTER 4 UPDATE_ENDED_INTERRUPT_FLAG 1=A Time and Date update has completed since the last time this reg- ister was read. This bit displays status regardless of the Update- Ended Interrupt Enable bit in Register B. Presentation of this sta- tus indicates that the Time and Date registers will be valid and sta- ble for over 999ms 0=A Time and Data update has not completed since the last time this register was read This bit is automatically cleared by every Read access to this register. RC 0b RTC_R ST 3:0 Reserved R - - Offset 0Dh Bits Description Type Default Reset Event 7:6 Reserved R - - 5:0 DATE_ALARM This field, if set to a non-zero value, will inhibit the Alarm interrupt unless this field matches the contents of the Month register also. If this field contains 00h (default), it represents a don’t-care, allowing more frequent alarms. R/W 00h RTC_R ST Offset 10h Bits Description Type Default Reset Event 7:4 Reserved R - - 3 ALARM_ENABLE 1=Enables the Alarm features 0=Disables the Alarm features R/W 0b RTC_R ST 2 Microchip Reserved R/W 0b RTC_R ST 1 SOFT_RESET A ‘1’ written to this bit position will trigger the RTC_RST reset, reset- ting the block and all registers except this one and the Test Register. This bit is self-clearing at the end of the reset, one cycle of LPC Bus Clock later, and so requires no waiting. R/W 0b VBAT_ POR 0 BLOCK_ENABLE This bit must be ‘1’ in order for the block to function internally. Regis- ters may be initialized first, before setting this bit to ‘1’ to start opera- tion. R/W 0b RTC_R ST Offset 0Ch Bits Description Type Default Reset Event |
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