MEC1322 datasheet(86/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 86

 2014 - 2015 Microchip Technology Inc.

The Sample phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks

equal to the IRQ/Data Frame times three, minus one e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, then the

sample phase is {(6 x 3) - 1 = 17} the seventeenth clock after the rising edge of the Start Pulse.

The SIRQ data frame will now support IRQ2 from a logical device; previously SERIRQ Period 3 was reserved for use

by the System Management Interrupt (LSMI#). When using Period 3 for IRQ2, the user should mask off the SMI via the

ESMI Mask Register. Likewise, when using Period 3 for LSMI#, the user should not configure any logical devices as

using IRQ2.

SERIRQ Period 14 is used to transfer IRQ13. Each Logical devices will have IRQ13 as a choice for their primary inter-

rupt.

STOP CYCLE CONTROL

Once all IRQ/Data Frames have completed, the host controller will terminate SERIRQ activity by initiating a Stop Frame.

Only the host controller can initiate the Stop Frame. A Stop Frame is indicated when the SERIRQ is low for two or three

clocks. If the Stop Frame’s low time is two clocks, then the next SERIRQ cycle’s sampled mode is the Quiet mode; and

any SERIRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s

pulse. If the Stop Frame’s low time is three clocks, then the next SERIRQ cycle’s sampled mode is the continuous mode,

and only the host controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop

Frame’s pulse.

5.8.4.4

Latency

Latency for IRQ/Data updates over the SERIRQ bus in bridge-less systems with the minimum IRQ/Data Frames of 17

will range up to 96 clocks (3.84

μS with a 25 MHz LCLK or 2.88μs with a 33 MHz LCLK).

5.8.4.5

EOI/ISR Read Latency

Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an

EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host

interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to

delay EOIs and ISR Reads to the interrupt controller by the same amount as the SERIRQ Cycle latency in order to

ensure that these events do not occur out of order.

TABLE 5-11:

SERIRQ SAMPLING PERIODS

SERIRQ Period

Signal Sampled

# of Clocks Past Start

1Not Used

2IRQ1

3IRQ2

4IRQ3

5IRQ4

6IRQ5

7IRQ6

8IRQ7

9IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

Note:

If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary

or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asyn-

chronous buses.

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