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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MEC1322 데이터시트(PDF) 95 Page - Microchip Technology |
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MEC1322 데이터시트(HTML) 95 Page - Microchip Technology |
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95 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 95 MEC1322 5.11.1 LPC BUS MONITOR REGISTER 5.11.2 HOST BUS ERROR REGISTER TABLE 5-21: EC-ONLY REGISTER SUMMARY Offset Register Name 04h LPC Bus Monitor Register 08h Host Bus Error Register 0Ch EC SERIRQ Register 10h EC Clock Control Register 14h MCHP Test Register 18h MCHP Test Register 20h BAR Inhibit Register 24h MCHP Reserved 28h MCHP Reserved 2Ch MCHP Reserved 30h LPC BAR Init Register Note: MCHP Reserved registers are read/write registers. Modifying these registers may have unwanted results. Offset 04h Bits Description Type Default Reset Event 31:2 RESERVED RES - - 1 LRESET_STATUS This bit reflects the state of the LRESET# input pin. The LRE- SET_Status is the inverse of the LRESET# pin. When the LRESET_Status bit is ‘0b’, the LRESET# input pin is de- asserted (that is, the pin has the value ‘1b’). When the LRESET_Sta- tus bit is ‘1b’, the LRESET# input pin is asserted (that is, the pin has the value ‘0b’). R0h VCC1_R ESET 0 MCHP Reserved R 0h VCC1_R ESET Offset 08h Bits Description Type Default Reset Event 31:8 ErrorAddress[23:16] This 24-bit field captures the 24-bit internal address of every LPC transaction whenever the bit LPC_INTERNAL_ERR in this register is 0. When LPC_INTERNAL_ERR is 1 this register is not updated but retains its previous value. When bus errors occur this field saves the address of the first address that caused an error. R0h VCC1_R ESET 5DMA_ERR This bit is set to 1 whenever EN_INTERNAL_ERR is 1 and an LPC DMA access causes an internal bus error. Once set, it remains set until cleared by being written with a 1. R/WC 0h VCC1_R ESET |
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