MEC1322 datasheet(60/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 60

 2014 - 2015 Microchip Technology Inc.

3.9.7

SYSTEM SLEEP CONTROL REGISTER (SYS_SLP_CNTRL)

The System Sleep States shown in Table 3-10 and determined by the bits in this register, are only entered if all blocks

are sleeping; that is, if the sleep enable bits are set for all blocks and no clocks are required.

14 ACPI EC 1 Clock Required

0: block does NOT need clocks.

1: block requires clocks.

R0h

VCC1_R

ESET

13 ACPI EC 0 Clock Required

0: block does NOT need clocks.

1: block requires clocks.

R0h

VCC1_R

ESET

12 GLBL_CFG Clock Required

0: block does NOT need clocks.

1: block requires clocks.

R-

VCC1_R

ESET

11:2 RESERVED

RES

1 UART 0 Clock Required

0: block does NOT need clocks.

1: block requires clocks.

R-

VCC1_R

ESET

0 LPC Clock Required

0: block does NOT need clocks.

1: block requires clocks.

R-

VCC1_R

ESET

Offset

18h

Bits

Description

Type

Default

Reset

Event

31:3 RESERVED

RES

2 Core regulator standby

0: keep regulator fully operational when sleeping.

1: standby the regulator when sleeping. Allows enough power for

chip static operation for memory retention.

R/W

VCC1_R

ESET

1 Ring oscillator output gate

0: keep ROSC ungated when sleeping.

1: gate the ROSC output when sleeping.

R/W

VCC1_R

ESET

0 Ring oscillator power down

0: keep ROSC operating when sleeping.

1: disable ROSC when sleeping. Clocks will start on wakeup, but

there is a clock lock latency penalty.

R/W

VCC1_R

ESET

Offset

14h

Bits

Description

Type

Default

Reset

Event

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