MEC1322 datasheet(272/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 272

 2014 - 2015 Microchip Technology Inc.

22.0 SMBUS INTERFACE

22.1

Introduction

The MEC1322 SMBus Interface includes one instance of the SMBus controller core. This chapter describes aspects of

the SMBus Interface that are unique to the MEC1322 instantiations of this core; including, Power Domain, Resets,

Clocks, Interrupts, Registers and the Physical Interface. For a General Description, Features, Block Diagram, Func-

tional Description, Registers Interface and other core-specific details, see

Ref [1] (note: in this chapter, italicized text

typically refers to SMBus controller core interface elements as described in Ref [1]).

22.2

References

SMBus Controller Core Interface, Revision 3.4, Core-Level Architecture Specification, SMSC, 7/16/12

22.3

Terminology

There is no terminology defined for this chapter.

22.4

Interface

This block is designed to be accessed externally via the pin interface and internally via a registered host interface. In

addition, this block is equipped with

22.5

Signal Description

The Signal Description Table lists the signals that are typically routed to the pin interface.

FIGURE 22-1:

I/O DIAGRAM OF BLOCK

TABLE 22-1:

SIGNAL DESCRIPTION TABLE

Name

Direction

Description

SMB_DAT0

Input/Output

SMBus Data Port 0

SMB_CLK0

Input/Output

SMBus Clock Port 0

SMB_DAT1

Input/Output

SMBus Data Port 1

SMB_CLK1

Input/Output

SMBus Clock Port 1

Note:

The SMB block signals that are shown in Table 22-1 are routed to the SMB pins as listed in Table 22-2.

Signal Description

SMBus Interface

Interrupts

Power, Clocks and Reset

Host Interface

DMA Interface

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