MEC1322 datasheet(171/456 Pages) MICROCHIP

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DS00001719D-page 171

MEC1322

13.5

Signal Description

Table 13-1, "ACPI PM1 Signal Description Table" lists the signals that are typically routed to the pin interface.

13.6

Host Interface

The registers defined for the ACPI PM1 Block Interface are accessible by the various hosts as indicated in Section

13.11, "Runtime Registers".

13.7

Power, Clocks and Resets

This section defines the Power, Clock, and Reset parameters of the block.

13.7.1

POWER DOMAINS

13.7.2

CLOCKS

This section describes all the clocks in the block, including those that are derived from the I/O Interface as well as the

ones that are derived or generated internally.

13.7.3

RESETS

13.8

Interrupts

This section defines the Interrupt Sources generated from this block.

TABLE 13-1:

ACPI PM1 SIGNAL DESCRIPTION TABLE

Name

Direction

Description

EC_SCI#

Output

Any or all of the PWRBTN_STS, SLPBTN_STS, and RTC_STS bits

in the Power Management 1 Status 2 Register can assert the

EC_SCI# pin if enabled by the associated bits in the Power Man-

agement 1 Enable 2 Register register. The EC_SCI_STS bit in the

EC-Only Registers register can also be used to generate an SCI on

the EC_SCI# pin.

TABLE 13-2:

POWER SOURCES

Name

Description

VCC1

This power well sources the registers and logic in this block.

TABLE 13-3:

CLOCKS

Name

Description

48 MHz Ring Oscillator

This clock signal drives selected logic (e.g., counters).

TABLE 13-4:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal resets all of the registers and logic in this block.

TABLE 13-5:

EC INTERRUPTS

Source

Description

ACPIPM1_CTL

This Interrupt is generated to the EC by the Host writing to the Power

Management 1 Control 2 Register register

ACPIPM1_EN

This Interrupt is generated to the EC by the Host writing to the Power

Management 1 Enable 2 Register register

ACPIPM1_STS

This Interrupt is generated to the EC by the Host writing to the Power

Management 1 Status 2 Register register

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