M95040-DRMF3TP datasheet(14/41 Pages) STMICROELECTRONICS

14 / 41 page

Instructions

M95040-A125 M95040-A145

14/41

DocID024225 Rev 6

Instructions

Each command is composed of bytes (MSBit transmitted first), initiated with the instruction

byte, as summarized in Table 5.

If an invalid instruction is sent (one not contained in Table 5), the device automatically enters

a Wait state until deselected.

For read and write commands to memory array and Identification Page, the address is

defined by two bytes as explained in Table 6.

Table 5. Instruction set

Instruction

Description

Instruction

format

WREN

Write Enable

0000 X110(1)

1. X = Don’t Care.

WRDI

Write Disable

0000 X100(1)

RDSR

Read Status Register

0000 X101(1)

WRSR

Write Status Register

0000 X001(1)

READ

Read from Memory Array

0000 A8011(2)

2. A8 = 1 for the upper half of the memory array, and 0 for the lower half.

WRITE

Write to Memory Array

0000 A8010(2)

RDID

Read Identification Page

1000 0011

WRID

Write Identification Page

1000 0010

RDLS

Reads the Identification Page lock status.

1000 0011

LID

Locks the Identification page in read-only mode.

1000 0010

Table 6. Significant bits within the address byte(1)(2)

Instructions

Bit b3 of the instruction byte

LSB Address byte

READ or

WRITE

xxxxxx

RDID or

WRID

000000

000

RDLS or

LID

000000

10000

000

1. A: Significant address bit.

2. x: bit is Don’t Care.

M95040-DRMF3TP 데이터시트(PDF) 14 Page - STMicroelectronics

M95040-DRMF3TP 데이터시트(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

데이터시트 다운로드

링크 URL