M95040-DRMF3TP datasheet(40/41 Pages) STMICROELECTRONICS

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Revision history

Table 19. Document revision history

Date

Revision

Changes

05-Apr-2013

Initial release.

05-Sep-2013

Added WFDFPN8 (MF) package.

Removed UFDFPN8 (MLP8) package.

Updated:

– Section 4.4: Write Status Register (WRSR): replaced “Bits b7, b6,

b5, b4 are always read as 0” by “Bits b7, b6, b5, b4 are always

read as 1”.

– Note (1) under Table 7: Absolute maximum ratings.

11-Dec-2013

Updated Figure 24: WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm

pitch very very thin fine pitch dual flat package outline.

Document status changed from “Preliminary Data” to “Production

Data”.

Data retention modified from “40 years at 50 °C” to “50 years at

125 °C”“.

26-Sept-2014

Updated Note 2 below Table 7: Absolute maximum ratings.

Updated Table 13: DC characteristics (voltage range R, temperature

range 3).

Updated Table 17: WFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch

very very thin fine pitch dual flat package mechanical data.

Updated Table 18: Ordering information scheme.

Added Note 2 below Figure 24: WFDFPN8 (MLP8) – 8-lead, 2 x

3 mm, 0.5 mm pitch very very thin fine pitch dual flat package

outline.

12-Jan-2015

Updated Table 17: WFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch

very very thin fine pitch dual flat package mechanical data

Updated Figure 24: WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm

pitch very very thin fine pitch dual flat package outline

Added paragraph: Engineering samples on page 39

16-Feb-2016

Updated

– Section 9: Package mechanical data

–VCC min value.

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