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M95040-DRMF3TP 데이터시트(PDF) 31 Page - STMicroelectronics

부품명 M95040-DRMF3TP
상세설명  Automotive 4-Kbit serial SPI bus EEPROMs
PDF  41 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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M95040-DRMF3TP 데이터시트(HTML) 31 Page - STMicroelectronics

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M95040-A125 M95040-A145
DC and AC parameters
40
Table 14. AC characteristics
Symbol
Alt.
Parameter
Min. Max. Min. Max. Min. Max.
Unit
Test
conditions
specified in
Table 10
Test
conditions
specified in
Table 9 and
Table 10
Test
conditions
specified in
Table 11
fC
fSCK Clock frequency
-
5
-
10
-
20
MHz
tSLCH
tCSS1 S active setup time
60
-
30
-
15
-
ns
tSHCH
tCSS2 S not active setup time
60
-
30
-
15
-
tSHSL
tCS
S deselect time
90
-
40
-
20
-
tCHSH
tCSH S active hold time
60
-
30
-
15
-
tCHSL
S not active hold time
60
-
30
-
15
-
tCH(1)
tCLH Clock high time
80
-
40
-
20
-
tCL(1)
tCLL Clock low time
80
-
40
-
20
-
tCLCH(2)
tRC
Clock rise time
-2-2-2
µs
tCHCL(2)
tFC
Clock fall time
-
2
-
2
-
2
tDVCH
tDSU Data in setup time
20
-
10
-
5
-
ns
tCHDX
tDH
Data in hold time
20
-
10
-
10
-
tHHCH
Clock low hold time after HOLD not active
60
-
30
-
15
-
tHLCH
Clock low hold time after HOLD active
60
-
30
-
15
-
tCLHL
Clock low set-up time before HOLD active
0-0-0
-
tCLHH
Clock low set-up time before HOLD not
active
0-0-0
-
tSHQZ(2)
tDIS
Output disable time
-
80
-
40
-
20
tCLQV(3)
tV
Clock low to output valid
-
80
-
40
-
20
tCLQX
tHO
Output hold time
0
-
0
-
0
-
tQLQH(2)
tRO
Output rise time
-
20
-
20
-
20
tQHQL(2)
tFO
Output fall time
-
20
-
20
-
20
tHHQV
tLZ
HOLD high to output valid
-
80
-
40
-
20
tHLQZ(2)
tHZ
HOLD low to output high-Z
-
80
-
40
-
20
tW
tWC
Write time
-4-4-4
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3. tCLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, tCL must be equal to
(or greater than) tCLQV+tSU.



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