POWERSTEP01 datasheet(39/92 Pages) STMICROELECTRONICS

39 / 92 page

DocID025022 Rev 5

39/92

powerSTEP01

Phase current control: voltage mode

8.1

PWM sinewave generators

The two voltage sinewaves applied to the stepper motor phases are generated by two PWM

modulators.

The PWM frequency (fPWM) is proportional to the oscillator frequency (fOSC) and can be

obtained through the following formula:

Equation 3

'N' is the integer division factor and 'm' is the multiplication factor. 'N' and 'm' values can be

programmed by F_PWM_INT and F_PWM_DEC parameters in the CONFIG register (see

Table 47 on page 68 and Table 48 on page 69).

Available PWM frequencies are listed in Section 11.1.27 on page 66 from Table 49 on

page 69 toTable 52 on page 70.

8.2

Sensorless stall detection

The powerSTEP01 is able to detect a motor stall caused by an excessive load torque. When

the motor is driven using the voltage mode approach, a stall condition corresponds to an

unexpected increase of the phase current. Imposing a current threshold slightly above the

operative current, it is possible to detect the stall condition without speed or position

sensors.

The powerSTEP01 measures the load current of each phase sensing the VDS voltage of the

low-side power MOSFETs. When any of the VDS voltages rise over the programmed

threshold, the STEP_LOSS_X flag in the STATUS register of the respective bridge

(STEP_LOSS_A or STEP_LOSS_B) is forced low. The failure flag is kept low until the VDS

voltages fall below the programmed threshold and a GetStatus command is sent to the

device (Section 11.1.27 and Section 11.2.20 on page 82).

The stall detection threshold can be programmed in one of 32 available values ranging from

31.25 mV to 1 V with steps of 31.25 mV (see Section 11.1.22 on page 61).

Stall detection comparators are disabled, in order to avoid wrong voltage measurements, in

the following cases:



The respective half-bridge is in high impedance state (both MOSFETs forced off).



The respective half-bridge is commutating.



The respective half-bridge is commutated and the programmed blanking time has not

yet elapsed.



The respective low-side gate is turned off.

8.3

Low speed optimization

When the motor is driven at a very low speed using a small driving voltage, the resulting

phase current can be distorted. As a consequence, the motor position is different from the

ideal one (see Figure 16).

The device implements a low speed optimization in order to remove this effect.

fPWM

fOSC

512 N



------------------ m



POWERSTEP01 데이터시트(PDF) 39 Page - STMicroelectronics

POWERSTEP01 데이터시트(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL