ST2100 datasheet(12/39 Pages) STMICROELECTRONICS

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Architecture description

ST2100

12/39

DocID025777 Rev 1

3.6

High-speed connectivity subsystem



Ethernet 10/100 MAC with MII interface (IEEE 802.3), with external PHY

–

RevMII (supporting 25 and 50 MHz clock frequencies)

–

IEEE 802.1-AS and 802.1-Qav for audio video (AV) traffic



USB 2.0 (high-full-low speed) port with integrated PHY able to work as a host or

device. The PHY is embedded.

–

One USB host controller compatible with USB 2.0 high-speed specification

managing a single port. The peripheral has a dedicated channel to the multiport

memory controller and a dedicated slave port for CPU programming (OHCI and

EHCI).

–

One USB device compatible with USB 2.0 high-speed specifications. A dedicated

channel connects the peripheral with the multiport memory controller and registers

and an internal FIFO are accessible from the CPU through the main AHB bus.

A USB plug detector block is also available to detect the presence of the VBUS

voltage.

3.7

Low-speed connectivity subsystem



Two independent UARTs supporting hardware flow control up to 460.8 Kbits/s



Fast IrDA controller with a speed rate from 9.6 Kbits/s to 4 Mbits/s (SIR/MIR/FIR)



One synchronous “Serial Port Interface” (SPI) controller capable of operating as

a master or a slave (Motorola - Texas Instruments - National Semiconductor) with

a speed (data) rate up to 20 Mbits/s



One I2C (also known as a digital audio interface) controller capable of operating in

master and slave mode and covering all the possible data rates (high, fast and low)



JPEG codec accelerator (1 clock per pixel)



8 Kbytes of static RAM



“Flexible Static Memory Controller” (FSMC) supporting:

–

Asynchronous parallel NAND and NOR Flash memories

–

Synchronous and asynchronous SRAM



Two independent “Controller Area Network” (CAN) interfaces compliant with CAN

protocol version 2.0 parts A and B (up to 1 Mbit/s).

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