L9662 datasheet(24/80 Pages) STMICROELECTRONICS

24 / 80 page

Electrical specifications

L9662

24/80

DocID028325 Rev 1

2.4.4

SPI timing

All SPI timing is performed with a 150 pF load on MISO unless otherwise noted

4.9V

 VDD  5.1V; 7V  VRESX  37V; 7V  VSDIAG  37V; (VSATS + 6V)  VSYNC  25V; 5V

 VSATS  14V; FEN1 = FEN2 = FEN3 = FEN4 = VDD; R_REF = 10K, ±1%, 100PPM; -

40°C

 TA  +95°C; unless other specified.

Table 9. SPI timing - DC electrical characteristics

No.

Symbol

Parameter

Min.

Typ.

Max.

Unit

fop

Transfer frequency

5.50

MHz

tSCK

SCLK, SCLK_S period

181

tLEAD

Enable lead time

tLAG

Enable lag time

tSCLKHS

SCLK, SCLK_S high time

tSCLKLS

SCLK, SCLK_S low time

tSUS

MOSI, MOSI_S input setup time

tHS

MOSI, MOSI_S input hold time

MISO, MISO_S access time

tDIS (1)

MISO, MISO_S disable time

100

tVS

MISO, MISO_S output valid time

tHO (1)

MISO, MISO_S output hold time

tRO

Rise Time (design information)

tFO

Fall Time (design information)

tCSN

CS_D, CS_S negated time

640

tCLKN

Time between CS rising edge and first transition

of SCLK must be higher than tCLKN. It happens

when multiple L9662 are connected to the same

SCLK and MOSI but with different chip select.

500

1. Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance

on the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable

time, and minimum capacitance on MISO is the worst case for output hold time.

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