L9662 datasheet(48/80 Pages) STMICROELECTRONICS

48 / 80 page

Functional description

L9662

48/80

DocID028325 Rev 1

STB/STG bit definition with MOSI D11:D9=011 (High side safing)

HSS1:HSS0 bits, see table below

STB/STG bit definition with MOSI D11:D9=010 (VRESx supply voltage)

VR1:VR0 bits, see table below

STB/STG bit definition with MOSI D11:D9=101 (High squib resistance)

HSR bit

Bit used for indicating leakage to ground.

0 = Squib Resistance below RSQHIZ

1 = Squib Resistance above RSQHIZ

Bits D6

Fault present prior to running LS FET or HS FET test (diagnostics

aborted)

0 = Normal

1 = Test not run - Fault present (FEN in incorrect state, short

to battery or ground)

Bits D5

Bit definition based on diagnostic selection.

FT bit Read Only - Used for LS FET or HS FET diagnostics

and is the status of the FET timer

0 = FET timer not active

1 = FET timer active

SQP bit: Squib Pin to be tested during short to

battery/ground diagnostics

0 = SQBLx pin test

1 = SQBHx pin test

Bits D4

Used to disable IPD on all channels

0 = IPD active as indicated;

– Active for all channels except the one under test when

running Short to Battery/Ground and short between loops

Diagnostics and LS/HS FET test

– Active for all channels when running Stop Diagnostic,

Table 24. Diagnostic mode HSS selection

Condition

HSS1

HSS0

(VSDIAG-VRESx) < VHSSSHORT_th

VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th

VHSSOPEN_th < (VSDIAG-VRESx)

Table 25. Diagnostic mode VRESx selection

Condition

VR1

VR0

VRESx < VVRESXLO_th

VVRESXLO_th < VRESx < VVRESXHI_th

VVRESXHI_th < VRESx

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