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VD5377 데이터시트(PDF) 54 Page - STMicroelectronics |
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VD5377 데이터시트(HTML) 54 Page - STMicroelectronics |
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54 / 88 page ![]() Image capture VD5377 54/88 Doc ID 022952 Rev 2 9 Image capture 9.1 I2C image capture The chip can acquire a single frame coming from the image array (either CDS, exposed or black frame), store it internally (in RAM), and deliver its 400 pixels through I2C registers. A maximum of 105 frames per second can be achieved in this mode. The timing diagram (Figure 23) describes the sequence of steps carried out within a complete frame in I2C frame dump mode. Figure 23. I2C frame dump timing diagram Table 32 lists the registers related to the control of the I2C frame dump mode. framedump_en framedump_ready framedump_pixdata framedump_done black DMIB out Actual2 RAM address CDS out 0 1 2 3 398 399 pixel address exposed exposed - black Actual2 RAM R/W# 0 ... 399 0 1 2 3 398 399 1 I2C coms 2 3 tsetup > 250us tframe > 9.4ms 1: Startup sequence of I2C frame dump mode 2: I2C multiple read of 400 bytes 3: Exit sequence of I2C frame dump mode 0 0: Init sequence of I2C frame dump mode |
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