RF430CL331HIPWR datasheet(32/60 Pages) TI1

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Stores the packet in the buffer

1.) Acknowledges the request

over RF

2.) Issues the interrupt

Reader (PCD)

RF430CL331H (PICC)

Reads the PICC

data buffer while

the next RF

transmission is

occurring

Host Controller

INTO

Interrupt (Second)

PCD sends the File Write

request

Decides whether to continue

writing more data

RF (First)

If necessary

RF430CL331H

SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

www.ti.com

Figure 5-15. Write System Flow (Nonblocking)

1. PCD procedure:

(a) Issues a Capability Container or a NDEF File Write (or Update Binary) command.

2. RF430CL331H procedure:

(a) Receives the RF Update Binary packet.

(b) Automatically responds with a successful acknowledgment: SW1 = 90h and SW2 = 00h.

(d) Issues the General Type 4 request interrupt.

(e) Waits for a new Update Binary packet to be transmitted to.

3. Host controller procedure:

(a) Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).

(b) The source of the interrupt is the General Type 4 request.

and the Type 4 Command field examined to determine what Type 4 command has been received.

(d) The result is an Update Binary command.

(e) The NDEF File Identifier register (see Section 5.11.7) may be read, but it is not necessary as it is

always the file that the last Select command selected.

(f) Read the Buffer Start register (see Section 5.11.11) to determine where in the buffer of the

RF430CL331H to begin reading the stored data. Reading this register is unnecessary, as it is

always 0.

(g) Read the NDEF File Offset register (see Section 5.11.10) to determine at which index of the NDEF

or CC file the current data is starting.

(h) Read the NDEF Block Length register (see Section 5.11.9) to determine how much data is being

sent by the PCD in this packet.

(i) Read the data from the buffer of the RF430CL331H, starting at the index of 0, until the block length

supplied, updating the main file on the host controller.

(j) The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done

before setting the Interrupt Serviced field in the Host Response register.

(k) To complete servicing the Update Binary command interrupt, set the Interrupt Serviced field in the

Host Response register.

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