AD6635BBSLASHPCB datasheet(41/60 Pages) AD

41 / 60 page

REV. 0

AD6635

–41–

WAIT ensures that the amount of time the AD6635 needs to

wait to begin data transmission is at least equal to the minimum

amount of time the TigerSHARC is expecting it to wait. If the

PCLK of the AD6635 is out of phase with the PCLK of the

TigerSHARC and the argument to the ceil( ) function is an

integer, then WAIT must be strictly greater than the value given

in the above formula. If the LCLKs are in phase, the maximum

output data rate is

LCLK

TSHARC

£¥

otherwise, it is

LCLK

TSHARC

£¥

TigerSHARC Configuration

Since the AD6635 is always the transmitter in this link and the

TigerSHARC is always the receiver, the following values can be

programmed into the LCTL register for the link port used to

receive AD6635 output data. “User” means that the actual

Table IX. TigerSHARC LCTLx Register Configuration

VERE

SPD

User

LTEN

PSIZE

TTOE

CERE

LREN

RTOE

Table X. Channel Memory Map (Part 1)

Channel Address

Bit Width

Comments

00–7F

Coefficient Memory (CMEM)

128

20-Bit Memory

CHANNEL SLEEP

0: SLEEP Bit from EXT_ADDRESS 3

Soft_Sync Control Register

1: Hop

0: Start

Pin_SYNC Control Register

2: First SYNC Only

1: Hop_En

0: Start_En

Start Holdoff Counter

Start Holdoff Value

NCO Frequency Holdoff Counter

NCO_FREQ Holdoff Value

NCO Frequency Register 0

NCO_FREQ[15:0]

NCO Frequency Register 1

NCO_FREQ[31:16]

NCO Phase Offset Register

NCO_PHASE[15:0]

NCO Control Register

8–7: SYNC Input Select[1:0]

6: WB Input Select B/A

5–4: Input Enable Control

11: Clock on IEN Transition to Low

10: Clock on IEN Transition to High

01: Clock on IEN High

00: Mask on IEN Low

3: Clear Phase Accumulator on HOP

2: Amplitude Dither

1: Phase Dither

0: Bypass (A Input

Æ I-Path, B Æ Q)

89–8F

Unused

(C Input

ÆI-Path, D ÆQ)

MEMORY MAP

This section describes the memory maps for channel, memory,

and for the input and output control registers.

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