| 전자부품 데이터시트 검색엔진 |
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PC87391 데이터시트(PDF) 43 Page - National Semiconductor (TI) |
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PC87391 데이터시트(HTML) 43 Page - National Semiconductor (TI) |
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43 / 148 page ![]() 2.0 Device Architecture and Configuration (Continued) 43 www.national.com 2.10.7 SuperI/O Configuration 6 Register (SIOCF6) Write access to this register can be inhibited by setting bit 7. Activation of each logical device (bits 0-4) is also affected by bit 0 of the logical device Activate register, index 30h and bit 0 of the SIOCF1 register. Location: Index 26h Type: R/W 2.10.8 SuperI/O Revision ID Register (SRID) This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The Chip Rev field identity number the chip revision. Location: Index 27h Type: RO Bit 76543210 Name SIOCF6 Software Lock General-Purpose Scratch Reserved Serial Port 1 Disable Serial Port 2 Disable Parallel Port Disable FDC Disable Reset 00000000 Bit Description 7 SIOCF6 Software Lock. When this bit is set to 1 by software, it can be cleared only by hardware reset. 0: Write access to bits 0-6 of this register enabled (default) 1: Bits 6-0 of this register are RO 6-5 General-Purpose Scratch 4 Reserved 3 Serial Port 1 Disable 0: Enabled (default) 1: Disabled 2 Serial Port 2 Disable 0: Enabled (default) 1: Disabled 1 Parallel Port Disable 0: Enabled (default) 1: Disabled 0 FDC Disable 0: Enabled (default) 1: Disabled Bit 76543210 Name Chip ID Chip Rev Reset 0 0 0 XXXXX Bit Description 7-5 Chip ID. 4-0 Chip Rev. These bits identify the device revision. |
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