PC87391 datasheet(91/148 Pages) NSC

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5.0 Game Port (GMP) (Continued)

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5.3.5

Game Port Interrupt Enable Register (GMPIEN)

This register defines the conditions on which the Game Port asserts its interrupt request signal.

This register is functional only in Enhanced mode.

Location:

Offset 03h

Type:

R/W

Bit

76543210

Name

Device B

Button 1

IRQ Enable

Device B

Button 0

IRQ Enable

Device A

Button 1

IRQ Enable

Device A

Button 0

IRQ Enable

Reserved

Position

IRQ Event

Deﬁnition

Device B

Position

IRQ Enable

Device A

Position

IRQ Enable

Reset

00000000

Bit

Description

Device B Button 1 IRQ Enable. When set to 1, the Game Port issues an interrupt request in response to an

event triggered by Button 1 of Device B. When set to 0, Button 1 of Device B cannot cause interrupt requests to

be issued.

0: Disabled (default)

1: Enabled

Device B Button 0 IRQ Enable. Same as bit 7 of this register, but for Device B Button 0.

0: Disabled (default)

1: Enabled

Device A Button 1 IRQ Enable. Same as bit 7 of this register, but for Device A Button 1.

0: Disabled (default)

1: Enabled

Device A Button 0 IRQ Enable. Same as bit 7 of this register, but for Device A Button 0.

0: Disabled (default)

1: Enabled

Reserved

Position IRQ Event Deﬁnition Deﬁnes the event on which the position IRQ is asserted for both game devices.

0: Both X-Position Counter and Y-Position Counter are ready

1: Either X-Position Counter or Y-Position Counter is ready

Device B Position IRQ Enable. When set to 1, the Game Port issues an interrupt request when the position

reading of Device B is completed and the position counters can be read. When set to 0, no interrupt request is

issued in response to any change in the status of Device B position counters.

0: Disabled (default)

1: Enabled

Device A Position IRQ Enable. Same as bit 2 of this register, but for Device A.

0: Disabled (default)

1: Enabled

PC87391 데이터시트(PDF) 91 Page - National Semiconductor (TI)

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