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PC87391 데이터시트(PDF) 77 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC87391
상세설명  100-Pin LPC SuperI/O Devices for Portable Applications
PDF  148 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87391 데이터시트(HTML) 77 Page - National Semiconductor (TI)

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)
77
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3.4.2
GPIO Pin Event Routing (GPEVR) Register
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index
register, and the specific GPER register that reflects the routing configuration of the currently selected pin. For details on the
GPSEL register, refer to the
Device Architecture and Configuration chapter.
This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port this register
set is reserved, returns 0 on read and has no effect on port functionality.
Location:
Device specific
Type:
R/W
3.4.3
GPIO Port Runtime Register Map
Bit
76543210
Name
Reserved
GPIO Event
to SMI
Enable
GPIO Event
to IRQ
Enable
Reset
00000001
Bit
Description
7-2
Reserved
1
GPIO Event to SMI Enable. This bit is used to enable/disable the routing of the corresponding detected GPIO
event to SMI.
0: Disabled (default)
1: Enabled
0
GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding detected GPIO
event to IRQ.
0: Disabled
1: Enabled (default)
Offset
Mnemonic
Register Name
Type
Section
Device specific 1
1. The location of this register is defined in the
Device Architecture and Configuration chap-
ter in Section 2.15.1.
GPDO
GPIO Data Out
R/W
3.4.4
Device specific 1
GPDI
GPIO Data In
RO
3.4.5
Device specific 1
GPEVEN
GPIO Event Enable
R/W
3.4.6
Device specific 1
GPEVST
GPIO Event Status
R/W1C
3.4.7



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