STA400A datasheet(93/117 Pages) STMICROELECTRONICS

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STA400A

0x040A).

b3-b0:

0000

Reserved

0001

Reserved

0010

Reserved for Future Use

0011

Reserved for Future Use

0100

Reserved for Future Use

0101

PC Bitstream Interface #2

0110

PC Bitstream Interface #1

0111

FEC_RS (Reed-Solomon decoder)

1000

FEC_FPP (FEC Pre-Processing)

1001

FEC_VD

1010

TDM

1011

Reserved for Future Use

1100

Terrestrial Demodulator (MCM demodulator)

1101

Satellite Demodulator #2 (QPSK2)

1110

Satellite Demodulator #1 (QPSK1)

1111

IF Sampling

CLKDIV_CONF

- Master Clock Programmable Divider

This register sets the division factor (2,4 or 8) of the master clock applied to XTI/MCLK input. The divided clock

is available at CLKD output (pin 56).

b1- b0 : CLK_DIV

00 = MCLK/2

(CLKD frequency = 23.92MHz/2=11.96MHz)

01 = MCLK/4

(CLKD frequency = 23.92MHz/2=11.96MHz)

10 = MCLK/8

(CLKD frequency = 23.92MHz/2=11.96MHz)

11 = Disabled

(CLKD fixed to GND)

QPSK_BER_CTRL

- Satellite Demodulators BER Control

This register is used in functional test mode for B.E.R. Measurement after satellite demodulation, using an ex-

ternal serial BER Tester. The BER measurement is on the hard decided output symbol and the relative clock

available at the FTESTOUT interface (see SELTSTOUT Register description).

This register controls the interface operations to synchronize the BER Tester on the demodulated satellite sym-

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

TSTMUXCTL

040B

3-0

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

CLKDIV_CONF

040C

1-0

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