STA400A datasheet(53/117 Pages) STMICROELECTRONICS

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STA400A

FfCtrl_M

- Fine Frequency Control Register

If mrm_ff_fed_mean_en is set to ‘1’ the ouput of the FED is averaged over two adjacent mcm symbols. If

mrm_ff_lpf_sel is set to ‘1’ an IT1 controller is implemented, otherwise a pure I controller. The mrm_ff_alpha

value determines the integral part for both IT1 and I controller.

b5-b2:

mrm_ff_alpha

b1:

mrm_ff_lpf_set

b0:

mrm_ff_fed_mean_en

FfBeta_M

- Fine Frequency Loop Filter Beta Constant

If mrm_ff_lpf_sel is set to ‘1’ the mrm_ff_beta value sets the proportional part for the IT1 controller. For a pure

I controller mrm_ff_beta is not used.

BlkDetect_M

- Frequency Control Blockage Condition

During blockage (mrm_blockage_detect = ‘1’) the Frequency Control state is set to FREEZE. In that state the

frequency offset is held and no further actions are untertaken.

b0:

mrm_blockage_detect

InitDelay_M

- Fine Frequency Statup Delay

This register sets the number for which the Frequency Control remains within the INIT state before entering the

TRACKING state, i.e. the corresponding number of Fine Frequency estimates are discarded after external reset

or internal clear.

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

FfCtrl_M

011C

5-0

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

FfBeta_M

011D

7-0

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

BlkDetect_M

011F

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

InitDelay_M

0120

1-0

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