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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA400A 데이터시트(PDF) 26 Page - STMicroelectronics |
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STA400A 데이터시트(HTML) 26 Page - STMicroelectronics |
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26 / 117 page  STA400A 26/117 Read Operation (see Fig. 16) Current Byte Address Read For the current byte address read mode, following a START condition the master sends the device ad- dress with the RW bit set to 1. The STA400A acknowledges this and outputs the byte addressed by the internal byte address counter. The counter is then incremented or not depending on the auto incremental bit. The master does not ac- knowledge the received byte, but terminates the transfer with a STOP condition. Random Byte Address Read A dummy write is performed to load the byte address into the internal address counter. This is followed by another START condition from the master and the device address repeated with the RW bit set to 1. The STA400A acknowledges this and outputs the byte addressed by the internal byte address counter already loaded The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. Sequential Address Read This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA400A continues to output the next byte in sequence, providing that the auto incremental mode bit be set. To terminate the stream of bytes the master does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter auto- matically incremented after each byte output. Figure 15. Write Mode Sequence Figure 16. Read Mode Sequence DEV ACK START D97AU669 RW BYTE ACK BYTE ACK DATA IN ACK STOP BYTE WRITE DEV ACK START RW BYTE ACK BYTE ACK DATA IN ACK STOP MULTIBYT WRITE DATA IN ACK DEV ACK START D97AU670 RW DATA NO ACK STOP CURRENT ADDRESS READ DEV ACK START RW BYTE ACK BYTE ACK DEV ACK STOP RANDOM ADDRESS READ DATA NO ACK START RW DEV ACK START DATA ACK DATA ACK STOP SEQUENTIAL CURRENT READ DATA NO ACK DEV ACK START RW BYTE ACK BYTE ACK DEV ACK SEQUENTIAL RANDOM READ DATA ACK START RW DATA ACK NO ACK STOP DATA RW= HIGH |
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