STA400A datasheet(114/117 Pages) STMICROELECTRONICS

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STA400A

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9 TIMING DIAGRAMS

9.1 AC Characterictics (Guaranteed by Design)

Figure 17. Clocks and I/O Timing Diagram

Load Circuit: 50 pF to ground.

Symbol

Parameter

Min

Max

Unit

tWH

Clock High Pulse Width

nsec

tWL

Clock Low Pulse Width

nsec

tRXC

Rise Delay

(XTI/MCLK Clock Input to MCLKO Clock Output)

7nsec

tRXCN

Rise Delay

(XTI/MCLK Clock Input to MCLKON Clock Output)

nsec

tFXC

Fall Delay

(XTI/MCLK Clock Input to MCLKO Clock Output)

7nsec

tFXCN

Fall Delay

(XTI/MCLK Clock Input to MCLKON Clock Output)

9nsec

tSU

Input Set-up Time

nsec

tHOLD

Input Hold Time

nsec

tDXO

Output Data Valid Delay

nsec

IF2TD[9:0]

IF2SD[7:0]

MAI1

MDQ[7:0]

000000000

0000000000

000000000000000000

HOLD

RXC

FXCN

FXC

RXCN

XTI/MCLK

MCLKO

MCLKON

DATA(1)

DATA(2)

DATA(3)

DXO

DIGITAL OUTPUTS

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