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LP8501 데이터시트(PDF) 21 Page - Texas Instruments

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부품명 LP8501
상세설명  LP8501 Multi-Purpose 9-Output LED Driver
PDF  51 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

LP8501 데이터시트(HTML) 21 Page - Texas Instruments

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LP8501
www.ti.com
SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013
LP8501 Engine Programming
The LP8501 has three independent programmable lighting engines. All the lighting engines have their own
program memory block allocated by the user. Note that in order to access program memory the operation mode
needs to be LOAD Program, at least for one of the three lighting engines. Also note that one should not change
from RUN —mode directly to LOAD program. Correct sequence would be RUN (10) –> DISABLED (00) –>
LOAD (01).
Program execution is clocked with 32 768Hz clock. This clock can be generated internally, or an external 32 kHz
clock can be connected to CLK pin. Using external clock enables synchronization of LED timing to this clock
rather than to the internal clock.
The engines have different priorities; thus when more than one engine is controlling the same LED output: the
LED engine 1 has the highest priority, LED engine 2 second highest and LED engine 3 third highest.
Supported instruction set is listed in the tables below:
Table 1. LP8501 LED Driver Instructions
Inst.
Bit [15]
Bit
Bit
Bit
Bit
Bit
Bit [9]
Bit [8] Bit [7] Bit [6]
Bit
Bit [4] Bit [3]
Bit
Bit
Bit
[14]
[13]
[12]
[11]
[10]
[5]
[2]
[1]
[0]
pres
Ramp
0
cale
Step time
Sign
# of increments
Set PWM
0
1
0
0
0
0
0
0
PWM value
pres
Wait
0
cale
Time
0
0
0
0
0
0
0
0
0
Table 2. LP8501 LED Mapping Instructions
Inst.
Bit
Bit
Bit
Bit
Bit
Bit
Bit [9] Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
[15
[14]
[13]
[12]
[11]
[10]
]
mux_ld
1
0
0
1
1
1
0
0
0
SRAM address 0–95
_start
mux_ld
1
0
0
1
1
1
0
0
1
SRAM address 0–95
_end
mux_se 1
0
0
1
1
1
0
1
0
LED select
l
mux_clr 1
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
mux_in
1
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
c
mux_de 1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
c
mux_se 1
0
0
1
1
1
1
1
1
SRAM address 0–95
t
Table 3. LP8501 Branch Instructions
Inst.
Bit [15]
Bi t
Bit
Bit [12]
Bit
Bit
Bit [9] Bit [8] Bit [7]
Bit [6]
Bit
Bit
Bit [3]
Bit
Bit
Bit
[14]
[13]
[11]
[10]
[5]
[4]
[2]
[1]
[0]
Go to
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Start
Branch
1
0
1
Loop count
Step number
Int
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
End
1
1
0
Int
Reset
X
X
X
X
X
X
X
X
X
X
X
Trigger
1
1
1
Wait for a trigger
Send a trigger
X
Ext. trig
X
X
ENGI
ENGI
ENGI
Ext.
X
X
ENGI
ENG
ENG
X
NE3
NE2
NE1
trig
NE3
INE2
INE1
Copyright © 2008–2013, Texas Instruments Incorporated
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