 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
LP8501 데이터시트(PDF) 29 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LP8501 데이터시트(HTML) 29 Page - Texas Instruments |
|
|
29 / 51 page  ack from slave start MSB Chip Addr LSB SCL ack from slave w MSB Register Addr LSB rs r MSB Data LSB stop ack from slave nack from master repeated start data from slave SDA start id =32h w ack address = 3Fh ack rs r ack address 3Fh data nack stop MSB Chip Address LSB id = 32h start MSB Chip Addr LSB w ack MSB Register Addr LSB ack MSB Data LSB ack stop ack from slave ack from slave ack from slave SCL SDA start id = 32h w ack addr = 40h ack ack address 40h data stop ADR6 bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 MSB LSB 0 0 0 1 1 0 1 I 2 C Slave Address (chip address) LP8501 www.ti.com SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013 Figure 26. LP8501 Chip Address Figure 27. Write cycle (w = write; SDA = “0”) id = chip address = 32h for LP8501 When a READ function is to be accomplished, a WRITE function must precede the READ function, as show above. Figure 28. Read cycle (r = read; SDA = "1"), id = chip address = 32h for LP8501 Control Register Write Cycle • Master device generates start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = 0). • Slave device sends acknowledge signal if the slave address is correct • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master sends data byte to be written to the addressed register. • Slave sends acknowledge signal. • If master will send further data bytes, the slave’s control register address will be incremented by one after acknowledge signal. In order to reduce program load time LP8501 supports address auto increment. Register address is incremented after each 8 data bits. For example, the whole program memory page can be written in one serial bus write sequence. Note: serial bus address auto increment is not supported for register addresses from 16H to 1EH. • Write cycle ends when the master creates stop condition. Control Register Read Cycle • Master device generates a start condition. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: LP8501 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
