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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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P89LPC932BA 데이터시트(PDF) 47 Page - NXP Semiconductors |
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P89LPC932BA 데이터시트(HTML) 47 Page - NXP Semiconductors |
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47 / 60 page  Philips Semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80C51 core Product data Rev. 04 — 06 January 2004 47 of 60 9397 750 12379 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 11. Dynamic characteristics Table 9: AC characteristics Tamb =0 °Cto+70 °C for commercial, −40 °Cto+85 °C for industrial, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fOSC =12MHz Unit Min Max Min Max fRCOSC internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz fWDOSC internal Watchdog oscillator frequency 280 480 280 480 kHz fOSC oscillator frequency 0 12 - - MHz tCLCL clock cycle see Figure 22 83 - - - ns fCLKLP CLKLP active frequency 0 8 - - MHz Glitch filter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock tCHCX HIGH time see Figure 22 33 tCLCL − tCLCX 33 - ns tCLCX LOW time see Figure 22 33 tCLCL − tCHCX 33 - ns tCLCH rise time see Figure 22 -8 - 8 ns tCHCL fall time see Figure 22 -8 - 8 ns Shift register (UART mode 0) tXLXL serial port clock cycle time see Figure 21 16 tCLCL - 1333 - ns tQVXH output data set-up to clock rising edge see Figure 21 13 tCLCL - 1083 - ns tXHQX output data hold after clock rising edge see Figure 21 -tCLCL + 20 - 103 ns tXHDX input data hold after clock rising edge see Figure 21 -0 - 0 ns tDVXH input data valid to clock rising edge see Figure 21 150 - 150 - ns SPI interface fSPI operating frequency 2.0 MHz (master) - - - - MHz 2.0 MHz (slave) 0 2.0 0 2.0 MHz 3.0 MHz (master) - - - - MHz 3.0 MHz (slave) 0 3.0 0 3.0 MHz tSPICYC cycle time see Figures 23, 24, 25, 26 2.0 MHz (master) - - - - ns 2.0 MHz (slave) 500 - 500 - ns 3.0 MHz (master) - - - - ns 3.0 MHz (slave) 333 - 333 - ns |
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