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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3]

The RSTSRC register reflects the cause of the P89LPC932 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

TH0

Timer 0 HIGH

8CH

00

00000000

TH1

Timer 1 HIGH

8DH

00

00000000

TH2

CCU timer HIGH

CDH

00

00000000

TICR2

CCU interrupt control register

C9H

TOIE2

TOCIE2D TOCIE2C TOCIE2B TOCIE2A

-

TICIE2B

TICIE2A

00

00000x00

TIFR2

CCU interrupt flag register

E9H

TOIF2

TOCF2D

TOCF2C

TOCF2B

TOCF2A

-

TICF2B

TICF2A

00

00000x00

TISE2

CCU interrupt status encode

register

DEH

-

-

-

-

-

ENCINT.

2

ENCINT.

1

ENCINT.

0

00

xxxxx000

TL0

Timer 0 LOW

8AH

00

00000000

TL1

Timer 1 LOW

8BH

00

00000000

TL2

CCU timer LOW

CCH

00

00000000

TMOD

Timer 0 and 1 mode

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00

00000000

TOR2H

CCU reload register HIGH

CFH

00

00000000

TOR2L

CCU reload register LOW

CEH

00

00000000

TPCR2H

Prescaler control register

HIGH

CBH

-

-

-

-

-

-

TPCR2H.

1

TPCR2H.

0

00

xxxxxx00

TPCR2L

Prescaler control register

LOW

CAH

TPCR2L.

7

TPCR2L.

6

TPCR2L.

5

TPCR2L.

4

TPCR2L.

3

TPCR2L.

2

TPCR2L.

1

TPCR2L.

0

00

00000000

TRIM

Internal oscillator trim register

96H

-

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

FF

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR

addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary