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TNETV1002IDZHK 데이터시트(PDF) 68 Page - Texas Instruments

부품명 TNETV1002IDZHK
상세설명  Fixed-Point Digital Signal Processor
PDF  102 Pages
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TNETV1002IDZHK 데이터시트(HTML) 68 Page - Texas Instruments

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Electrical Specifications
58
June 2001 -- Revised December 2002
SPRS180C
6.7
Ready Timing for Externally Generated Wait-States
Table 6--12 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6--8,
through Figure 6--11).
Table 6--12. Ready Timing For Externally Generated Wait-States Timing Requirements†
MIN
MAX
UNIT
tsu(RDY)
Setup time, DSP_READY before DSP_CLKOUT low
5
ns
th(RDY)
Hold time, DSP_READY after DSP_CLKOUT low
3
ns
tv(RDY)MSTRB
Valid time, DSP_READY after DSP_MSTRB low‡
4H--11
ns
th(RDY)MSTRB
Hold time, DSP_READY after DSP_MSTRB low‡
4H
ns
tv(RDY)DSP_IOSTRB Valid time, DSP_READY after DSP_IOSTRB low‡
5H--11
ns
th(RDY)DSP_IOSTRB Hold time, DSP_READY after DSP_IOSTRB low‡
5H
ns
tv(MSCL)
Valid time, DSP_MSC low after DSP_CLKOUT low
1.5
11.5
ns
tv(MSCH)
Valid time, DSP_MSC high after DSP_CLKOUT low
1.5
11.5
ns
† The hardware wait-states can be used only in conjunction with the software wait-states to extend the bus cycles. To generate wait-states using
DSP_READY, at least two software wait-states must be programmed.
‡ These timings are included for reference only. The critical timings for DSP_READY are those referenced to DSP_CLKOUT.
DSP_MSC
DSP_MSTRB
DSP_READY
DSP_A[19:0]
DSP_CLKOUT
tv(MSCH)
tv(MSCL)
th(RDY)
th(RDY)MSTRB
tv(RDY)MSTRB
Wait State
Generated by
DSP_READY
Wait-States
Generated Internally
tsu(RDY)
Figure 6--8. Memory Read With Externally Generated Wait-States



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