TNETV1002IDZHK datasheet(10/102 Pages) TI1

10 / 102 page

Tables

June 2001 -- Revised December 2002

SPRS180C

Table

Page

6--20

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b and CLKXP = 0)

.......

6--21

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b and CLKXP = 0)

...

6--22

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b and CLKXP = 0)

.......

6--23

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b and CLKXP = 0)

...

6--24

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b and CLKXP = 1)

.......

6--25

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b and CLKXP = 1)

...

6--26

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b and CLKXP = 1)

.......

6--27

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b and CLKXP = 1)

...

6--28

Synchronous DRAM Timing Requirements

..............................................

6--29

Synchronous DRAM Switching Characteristics

...........................................

6--30

I2C Bus Device Switching Characteristics of the SDA and SCL Bus Lines

...................

6--31

I2C Bus Device Timing Requirements (STOP and START Conditions)

......................

6--32

I2C Bus Device Timing Requirements (Repeated START Condition)

........................

6--33

MII Timing Requirements (Receive)

....................................................

6--34

MII Timing Requirements (Transmit)

....................................................

6--35

ARM SRAM Switching Characteristics

..................................................

6--36

ARM SRAM Timing Requirements (Write)

...............................................

6--37

ARM SRAM Timing Requirements (Read)

...............................................

6--38

SPI Clock Switching Characteristics

....................................................

6--39

SPI Falling Edge Timing Requirements

.................................................

6--40

SPI Rising Edge Timing Requirements

.................................................

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